1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to an SRAM (static random access memory).
2. Description of the Related Art
The memory cell of the above SRAM constitutes a flip-flop circuit and comprises a driver transistor for holding data and a transfer transistor for selectively receiving a read current from a bit line.
To perform normal read/write, it is necessary to adequately secure the ratio of a saturation drain current of a driver transistor to a saturation drain current of a transfer transistor (.beta. ratio) shown by the following expression. EQU .beta. ratio=.beta.(driver)/.beta.(transfer).div.IDS(driver)/IDS(transfer)
For example, .beta. ratio is set to 3 to 4. The .beta. ratio is secured by making .beta.(transfer) smaller than .beta.(driver).
To secure the .beta. ratio, the following device design is performed. The saturation drain current is expressed as shown below. EQU IDS .varies. channel width//channel length
Therefore, the .beta. ratio is approximately expressed as follows: ##EQU1##
Wt: channel width of transfer transistor
LT: channel length of transfer transistor
Wd: channel width of driver transistor
Ld: channel length of driver transistor
Therefore, to secure the .beta. ratio at 3 to 4, the channel length of the transfer transistor is equalized and the channel width of the transfer transistor is set to 1/3 to 1/4 the channel width of the driver transistor. This is because the area occupied by the memory cell increases when the channel length of the transfer transistor is increased.
FIG. 1 is a top view for explaining a pattern layout of an SRAM having a memory cell comprising an transfer transistor, driver transistor, and load element according to the related art. In FIG. 1, an active region of the transfer transistor, an active region of the driver transistor, and a word line (hereinafter referred to as WL) made of a polycrystal-silicon film patterned like a strip are illustrated but a load element, a power supply line, and a bit line (hereafter referred to as BL) are not illustrated.
In FIG. 1, WL1 is a first branch word line which is made of a strip-shaped polycrystal-silicon film extending in a definite direction. WL2 is a second branch word line which is arranged in approximately parallel with the WL1 by keeping a certain interval from the WL1. And, a first active region 1a and a second active region, 1b are arranged in a region between the WL1 and WL2. The WL1 and WL2 are connected each other in a not-illustrated region to serve as a common WL in the memory cell.
Symbol 1a is a strip-shaped first active region formed in a semiconductor substrate, having a region perpendicular to the WL1 and a region, arranged between the WL1 and WL2 , parallel with the WL1 and WL2. The WL1 perpendicular to the first active region 1a serves as a gate electrode of a first transfer transistor T7. Symbol 1b is a strip-shaped second active region formed in the semiconductor substrate, having a region perpendicular to the WL2 and a region, arranged between the WL1 and WL2, parallel with the WL1 and WL2. The WL2 perpendicular to the second active region 1b serves as a gate electrode of a second transfer transistor T9.
Symbol 2a is a first gate electrode of a first driver transistor T8, which is arranged to perpendicularly intersect the first active region 1a arranged in parallel with the WL1 and WL2. The other end of the first gate electrode 2a is connected to the second active region 1b. Symbol 2b is a second gate electrode of a second driver transistor T10, which is arranged to perpendicularly intersect the second active region 1b. The other end of the second gate electrode 2b is connected to the first active region 1a.
Moreover, details of the above arrangement are described below. That is, a region including both the WL1 and the first active region la perpendicular to the WL1 corresponds to T7 and a region including both the first gate electrode 2a and the first active region 1a perpendicular to the first gate electrode 2a corresponds to T8. An opposite conductivity-type impurity is introduced into the semiconductor substrate of the first active region 1a at the both sides of the WL1 and at the both sides of the first gate electrode 2a to form two sets of source/drain regions (hereinafter referred to as S/D region.). Moreover, the semiconductor substrates under the WL1 and first gate electrode 2a serve as channel regions of T7 and T8 respectively.
A region including both the WL2 and the second active region 1b perpendicular to the WL2 corresponds to T9 and a region including both the second electrode 2b and the second active region 1b perpendicular to the second gate electrode 2b corresponds to T10. An opposite conductivity-type impurity is introduced into the semiconductor substrate of the second active region 1b at the both sides of the WL2 and at the both sides of the second gate electrode 2b to form two sets of the S/D regions. The semiconductor substrates under the WL2 and second gate electrode 2b serve as channel regions of T9 and T10 respectively.
However, when T8 and T10 are made finer in order to advance the integration level of an SRAM, it is necessary to decrease the channel widths of T7 and T9 in accordance with the decrease of T8 and T10 in size in order to secure the above .beta. ratio. However, there comes such a problem that it is difficult to stably form the channels because of the narrow channel effect.
To solve the problem, it is necessary to increase the channel lengths of T7 and T9. However, there arises such a problem that an area for forming a memory cell increases and the integration level cannot be advanced.